The present invention relates in general to packaging integrated circuits, and more particularly, to structures and methods for electrically interconnecting and absorbing stress between a first electrical structure and a second electrical structure, wherein the first and second structures may have different coefficients of thermal expansion.
The problem addressed herein relates to stresses on the input/output (I/O) bumps of Flip Chips, Chip Scale Packages, and interposers for Ball Grid Array (BGA) packages. Specifically, these bumps connect from the pads on, for example, a Flip Chip or Chip Scale Package to a printed circuit board by soldering to pads on the printed circuit board. The printed circuit board is usually an FR4-type board which has an expansion coefficient of 10 to 20 ppm per degree C. depending on the amount of copper wiring employed and other board configuration parameters. In comparison, a silicon integrated circuit (IC) chip has an expansion coefficient of 2-4 ppm per degree C. As a result of this mismatch, thermal stresses can be set up which tend to fatigue the bump or the material surrounding the bump. After several thermal cycles the solder or adjacent material can fail resulting in an open circuit.
The earliest known process of the type described above is the IBM C4 process in which small solder balls are built up directly on the pads of an IC chip. The chip is then inverted and soldered to pads on a circuit board. This process works well when the substrate is well matched to the silicon IC. Such substrates as silicon or alumina have expansion coefficients of 2 to 6 ppm. When this process is done on an FR4 substrate using large chips (1 to 2 cm) less than 100 thermal cycles can be achieved before failure. To minimize this effect, a process is often used where an epoxy material is caused to flow under the chip to bond the chip to the substrate. This distributes the stresses and increases the number of thermal cycles to failure by an order of magnitude. Two problems exist with this process. First, this so called under-fill process requires time consuming steps of deposition and vacuum flow followed by curing. Second, if a chip is bad it cannot be removed once the under-fill has been applied and cured.
Another alternative is to use solder balls which are large in diameter or height so that the differential expansion is amortized over the length of the solder and the 1% strain limit is not exceeded. (It has been found that if solder strain is kept below 1% during temperature cycling then the number of thermal cycles that the solder can endure without fatigue failure is in the 100 to 1000 cycle range.) The problem in this case is that large solder balls take up a large amount of space which is not usually available on the surface of an IC chip. Various techniques have been developed for screen printing large solder balls or columns but these have the same problem that the solder foot print is large and limits the number of I/O available for a given chip size. In addition, when the part is removed usually some solder remains on the circuit board and some solder remains on the part. This adds a requirement for completely cleaning the solder from the circuit board pads before replacing the part.
Another approach is provided by Tessera Inc. of San Jose, Calif., in which a Kapton xe2x80x9cflex circuitxe2x80x9d layer is placed over a compliant layer on the IC chip. The compliant layer decouples the chip from the Kapton xe2x80x9cflex circuitxe2x80x9d layer. The Kapton xe2x80x9cflex circuitxe2x80x9d connects to the circuit board but does not communicate the expansion differential back to the IC chip since the compliant layer is interspersed between the IC chip and the Kapton xe2x80x9cflex circuitxe2x80x9d. In the Tessera approach, wire or ribbon bonding is used to make connection from the edge of the Kapton circuit layer to the bond pads of the chip. This precludes wiring channels in the area above the bond pads of an IC and thereby limits the number of bond pads which can be accommodated. The approach is expensive because it is not well integrated. It really consists of several components: the Kapton circuit layer, the wire bond or ribbon interconnect, the compliant material and an encapsulant to hold the whole system together. This leads to expensive serial processing steps to connect up the package. (However, the approach does address the problem of thermal mismatch and Tessera chip scale packages can be attached to FR4 circuit boards without under-fill.)
To address the deficiencies of the above processes, presented herein are certain novel structures and methods of fabrication which maintain the strain on the solder or interconnection bumps between a first and second electrical structure to a level lower than the desired 1% level.
In view of the above, one object of this invention is to provide I/O bumps on, for example, a chip scale package or multichip module package with sufficient compliance that the packages can be readily mounted on a printed circuit board, such as a conventional printed circuit board, without requiring the use of under-fill between the package and the board.
Another object of this invention is to provide a chip scale package or multichip module package with the attributes of flip chip (small bumps, high I/O capability, and low inductance, high density interconnection), without requiring under-fill when mounting the package to a printed circuit board.
Still another object of the present invention is to provide I/O bumps on chip scale and multichip module packages which allow removal of the packages from a printed circuit board without leaving large differential solder residue.
A further object of the present invention is to provide an I/O bump for chip scale and multichip module packages which has sufficient compliance that temporary electrical contact to a circuit board can be made directly without use of an interposer or sockets.
Briefly summarized, the present invention comprises in one aspect a circuit structure which includes a support surface having at least one contact pad disposed thereon. A dielectric layer is disposed over the support surface and has at least one via opening exposing the at least one contact pad. At least one non-conductive compliant bump is disposed above the dielectric layer, and at least one metal layer is provided which includes metal over a surface of the at least one non-conductive compliant bump. The at least one metal layer facilitates electrical coupling of the metal over the surface of the at least one non-conductive compliant bump with the at least one contact pad on the support surface.
In another aspect, a circuit structure is provided which includes a support surface having at least one contact pad disposed thereon. A dielectric layer is disposed over the support surface and includes at least one via opening therein exposing the at least one contact pad. A metal layer is disposed over the dielectric layer and extends into the at least one via opening to electrically contact the at least one contact pad. The circuit structure further includes at least one mushroom-shaped conductive bump disposed above the dielectric layer and electrically coupling to the metal layer. Each mushroom-shaped conductive bump has a stem portion and a top portion, with the stem portion electrically coupling the top portion to the metal layer.
In yet another aspect, a method of fabricating a circuit structure is provided which includes: providing a support surface having at least one contact pad disposed thereon; disposing a dielectric layer over the support surface, and forming at least one via opening in the dielectric layer to expose the at least one contact pad; providing at least one non-conductive compliant bump over the dielectric layer; and forming at least one metal layer which includes metal over a surface of the at least one non-conductive compliant bump, and which facilitates electrical coupling of the metal over the surface of the at least one non-conductive compliant bump with the at least one contact pad of the support surface.
In a further aspect, provided herein is a method of fabricating a circuit structure which includes: providing a support surface having at least one contact pad formed thereon; disposing a dielectric layer above the support surface, and forming at least one via opening in the dielectric layer to expose the at least one contact pad; disposing a metal layer over the dielectric layer and extending into the at least one via opening to electrically contact the at least one contact pad; and providing at least one mushroom-shaped conductive bump above the dielectric layer and electrically coupled to the metal layer, wherein each mushroom-shaped conductive bump has a stem portion and a top portion, said stem portion electrically coupling said top portion to said metal layer.
To restate, provided herein are structures and methods which employ a compliant photo patternable polymer either as the core of an I/O bump or to provide compliance under a solid conductive bump. In either case, compliance is sufficient to absorb the expansion differential between, for example, a chip scale package and an FR4-type printed circuit board to which the package is solder mounted. The structures disclosed herein have the advantage of flip chip technology, but can be mounted directly on an FR4-type circuit board without the requirement for under-fill for reliability. Fabrication methods are disclosed for providing the structure directly on a wafer or for fabricating the structure in a panel of individual chips. Both single and multichip structures are disclosed. Also provided is a novel self-aligning solder mask in which the solder mask polymer is coated on the bump, and runs off the top of the bump leaving it exposed for subsequent plating of a solderable finish.
The structures and methods preferably employ a low elastic modulus and high ultimate elongation property material (LMHE dielectric). The disclosed material is photo patternable and can be patterned with a very short exposure time. Further, the material can be developed in thick sections with excellent resolution using simple dip tank development techniques as opposed to more complicated spray development techniques. The low modulus property essentially eliminates any stress on solder or other ball-type joints that interconnect, for example, packaged integrated circuit chips to a printed circuit board. The high elongation property allows the dielectric to stretch significantly without failure to the dielectric. Various structural configurations that make use of the LMHE dielectric material are described.